The present invention relates to a method for making semiconductor devices, particularly those that include fine feature structures.
To enable semiconductor devices to continue to scale downward, a commercially viable technique for patterning fine feature structures that are less than about 50 nm wide will be required. Current optical lithography techniques (e.g., those for defining vias and/or trenches to be filled with a conductive material using single or dual damascene processes) may not enable 50 nm features. Although 193 nm lithography may facilitate 90-110 nm patterns, variants of that technology that enable 50 nm, and smaller, features are not yet commercially available. Similarly, although the RELACS(trademark) process may serve to reduce via and trench size, that process may not currently enable structures that are less than 50 nm wide. (RELACS(trademark) is a trademark of the Mitsubishi Electronic Corporation. Materials for use in the RELACS(trademark) process are available from the AZ Electronic Materials division of Clariant International, Ltd.) Likewise, reducing via size by applying a special chemical treatment to a previously patterned photoresist layer to shrink the photoresist opening, prior to etching the via, does not appear to offer an acceptable process for defining 50 nm features.
Other proposed methods for reaching 50 nm either require sophisticated mask technology (e.g., phase-shift masks) or remain in the experimental stage (e.g., 157 nm optical lithography, EUV lithography, x-ray proximity lithography, and electron beam technology). Using advanced mask technology can significantly increase cost, and experimental methods are not yet practical for high volume manufacturing.
Accordingly, there is a need for a process for patterning fine feature structures, when making semiconductor devices. There is a need for such a process that enables 50 nm, and smaller, patterns to be formed using conventional lithography materials, tools and procedures. The present invention provides such a process.